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1WtEu@cr@TrwX@;rHf@fH@HSHHt$(HT$0HL$8LD$@LL$Ht7)D$P)L$`)T$p)$)$)$)$)$H$HH=f @&@HD$HD$ D$D$0HD$1sH=f HL$HھpH5f 
#rsfSrHt[É޿@SrHt[É޿@H\$Hl$HLd$HqD`DIcHHHrHHl$H$Ld$HfAH\$Hl$HHHv1H\$Hl$H$@fv@H%H3qHl$H\$HDH߾l@o	H\$Hl$HfF$H\$Hl$H1uxz4/v@H=HoHHPHHoH\$Hl$H2zH\$Hl$Hÿ{@1n>pHtM8tHn⿖@1nHM HU@LE1pHHpHHu1%qH@1HX@H@1zH@1kHl$Ld$H-cY L%\Y Ll$Lt$L|$H\$H8L)AIHIKmHt1@LLDAHH9uH\$Hl$Ld$Ll$ Lt$(L|$0H8ÐUHSHHX Ht`DHHHuH[]ÐHsH "%04x:%02x:%02x.%d [size=%u%s]non-64-bit32-bittype 3low-1M	Region %d: [virtual] I/O ports at %04lx<ignored><unassigned> [disabled]<invalid-64bit-slot>%08lx (%s, %sprefetchable)Expansion ROM at  [disabled by cmd]Slot:	Device:	Class:	%s
SVendor:	%s
SDevice:	%s
PhySlot:	%s
Rev:	%02x
ProgIf:	%02x
 -r%02x -p%02x "" "" %s: %s (rev %02x) (prog-if %02x [%s]	Subsystem: %s
slow??mediumfast (prefetchable)	Physical Slot: %s
	Latency: %d (%dns min%dns max, Cache Line Size: %d bytes	Flags: bus master, VGA palette snoop, stepping, fast Back2Back, 66MHz, user-definable features, %s devsel, latency %d, IRQ %d	BIST is running	BIST result: %02x
	I/O window %d: %08x-%08x%s
	Secondary status: SERR	<access denied to the rest>%02x:--versionlspci version 3.1.8-s: %s-d: %sInternal bug: Accessing non-read configuration byte at position %xlspci: Unable to read the standard configuration space header of device %04x:%02x:%02x.%d
	!!! Invalid class %04x for header type %02x
	!!! Unknown header type %02x
	Control: I/O%c Mem%c BusMaster%c SpecCycle%c MemWINV%c VGASnoop%c ParErr%c Stepping%c SERR%c FastB2B%c DisINTx%c
	Status: Cap%c 66MHz%c UDF%c FastB2B%c ParErr%c DEVSEL=%s >TAbort%c <TAbort%c <MAbort%c >SERR%c <PERR%c INTx%c
	Interrupt: pin %c routed to IRQ %d
	Bus: primary=%02x, secondary=%02x, subordinate=%02x, sec-latency=%d
	!!! Unknown I/O range types %x/%x
	I/O behind bridge: %08x-%08x
	!!! Unknown memory range types %x/%x
	Memory behind bridge: %08x-%08x
	!!! Unknown prefetchable memory range types %x/%x
	Prefetchable memory behind bridge: %08x-%08x
	Prefetchable memory behind bridge: %08x%08x-%08x%08x
	Secondary status: 66MHz%c FastB2B%c ParErr%c DEVSEL=%s >TAbort%c <TAbort%c <MAbort%c <SERR%c <PERR%c
	BridgeCtl: Parity%c SERR%c NoISA%c VGA%c MAbort%c >Reset%c FastB2B%c
		PriDiscTmr%c SecDiscTmr%c DiscTmrStat%c DiscTmrSERREn%c
	Memory window %d: %08x-%08x%s%s
	BridgeCtl: Parity%c SERR%c ISA%c VGA%c MAbort%c >Reset%c 16bInt%c PostWrite%c
	16-bit legacy interface ports at %04x
@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@P@@@@@0@@ @@@@@@@@@@@@@p@lspciKMGT\\\x%02xRead-onlyRead/writebadgoodlargesmallVital Product Data		End		Product Name: 		%s fields:
			[%c%c] %s: %d byte(s) free
		Not readable		No end tag foundExtended capabilityEngineering changesManufacture IDPart numberReservedRead-write areaSerial numberAsset tagVendor specificSystem specificUnknownchecksum %s, %d byte(s) reserved
		Unknown %s resource type %02x, will not decode more.
CP^@ECr@MN@PN@RV@RW@SN@YAȰ@VҰ@Y@@x%dunknownExpress (v%d) Legacy EndpointRoot Port (Slot%c)Upstream PortDownstream Port (Slot%c)PCI/PCI-X BridgeRoot Complex Event CollectorUnknown type %d, MSI %02x
			ExtTag%c AttnBtn%c AttnInd%c PwrInd%c RBE%c FLReset%cSlotPowerLimit %.3fW BrConfRtry%c		LnkCtl:	ASPM %s; RCB %d bytes		RootCap: CRSVisible%c
 ARIFwd%c
bridgesimple	Capabilities: <access denied>[%02x] <chain looped><chain broken>Power Management version %d
		Bridge: PM%c B3%c
AGP version %x.%x
		Address: %08x%08x  Data: %04x
CompactPCI hot-swap <?>PCI-X non-bridge devicePCI-X bridge device		Revision ID: %u.%02u
		Link Frequency 0: %s
		Link Frequency 1: %s
		Bus Number: %02x
		Link Frequency: %s
HyperTransport: SwitchHyperTransport: DirectRouteHyperTransport: VCSetHyperTransport: Retry ModeHyperTransport: #%02x
Hot-plug capableAGP3 <?>Secure device <?>		PBA: BAR=%d offset=%08x
SATA HBA v%d.%d BAR%d Offset=%08x
 InCfgSpace BAR??%d
PCI Advanced Features		AFCap: TP%c FLR%c
		AFCtrl: FLR%c
		AFStatus: TP%c
#%02x [%04x]
conv66MHz100MHz133MHz?4?5?6?78bit16bit[2]32bit4bit[6]N/C200MHz300MHz400MHz500MHz600MHz800MHz1.0GHz1.2GHz1.4GHz1.6GHz[a][b][c][d][e]Vend<1us<2us<4us<8us<16us<32us<64usunlimited<64ns<128ns<256ns<512nsL0sL0s L12.5GT/sDisabledL0s EnabledL0s L1 EnabledOnBlinkOffNot SupportedRange ARange BRange ABRange BCRange ABCRange BCDRange ABCD50us to 50ms50us to 100us1ms to 10ms16ms to 55ms65ms to 210ms260ms to 900ms1s to 3.5s4s to 13s17s to 64s-6dB-3.5dBNormal Operating RangePCI/PCI-X to PCI-Express BridgeRoot Complex Integrated Endpoint		DevCap:	MaxPayload %d bytes, PhantFunc %d, Latency L0s %s, L1 %s
		DevCtl:	Report errors: Correctable%c Non-Fatal%c Fatal%c Unsupported%c
			RlxdOrd%c ExtTag%c PhantFunc%c AuxPwr%c NoSnoop%c
			MaxPayload %d bytes, MaxReadReq %d bytes
		DevSta:	CorrErr%c UncorrErr%c FatalErr%c UnsuppReq%c AuxPwr%c TransPend%c
		LnkCap:	Port #%d, Speed %s, Width x%d, ASPM %s, Latency L0 %s, L1 %s
			ClockPM%c Surprise%c LLActRep%c BwNot%c
 Disabled%c Retrain%c CommClk%c
			ExtSynch%c ClockPM%c AutWidDis%c BWInt%c AutBWInt%c
		LnkSta:	Speed %s, Width x%d, TrErr%c Train%c SlotClk%c DLActive%c BWMgmt%c ABWMgmt%c
		SltCap:	AttnBtn%c PwrCtrl%c MRL%c AttnInd%c PwrInd%c HotPlug%c Surprise%c
			Slot #%d, PowerLimit %.3fW; Interlock%c NoCompl%c
		SltCtl:	Enable: AttnBtn%c PwrFlt%c MRL%c PresDet%c CmdCplt%c HPIrq%c LinkChg%c
			Control: AttnInd %s, PwrInd %s, Power%c Interlock%c
		SltSta:	Status: AttnBtn%c PowerFlt%c MRL%c CmdCplt%c PresDet%c Interlock%c
			Changed: MRL%c PresDet%c LinkState%c
		RootCtl: ErrCorrectable%c ErrNon-Fatal%c ErrFatal%c PMEIntEna%c CRSVisible%c
		RootSta: PME ReqID %04x, PMEStatus%c PMEPending%c
		DevCap2: Completion Timeout: %s, TimeoutDis%c		DevCtl2: Completion Timeout: %s, TimeoutDis%c		LnkCtl2: Target Link Speed: %s, EnterCompliance%c SpeedDis%c, Selectable De-emphasis: %s
			 Transmit Margin: %s, EnterModifiedCompliance%c ComplianceSOS%c
			 Compliance De-emphasis: %s
		LnkSta2: Current De-emphasis Level: %s
		Command: BaseUnitID=%u UnitCnt=%u MastHost%c DefDir%c DUL%c
		Command: BaseUnitID=%u UnitCnt=%u MastHost%c DefDir%c
		Link Control 0: CFlE%c CST%c CFE%c <LkFail%c Init%c EOC%c TXO%c <CRCErr=%x IsocEn%c LSEn%c ExtCTL%c 64b%c
		Link Control 0: CFlE%c CST%c CFE%c <LkFail%c Init%c EOC%c TXO%c <CRCErr=%x
		Link Config 0: MLWI=%1$s DwFcIn%5$c MLWO=%2$s DwFcOut%6$c LWI=%3$s DwFcInEn%7$c LWO=%4$s DwFcOutEn%8$c
		Link Config 0: MLWI=%s MLWO=%s LWI=%s LWO=%s
		Link Control 1: CFlE%c CST%c CFE%c <LkFail%c Init%c EOC%c TXO%c <CRCErr=%x IsocEn%c LSEn%c ExtCTL%c 64b%c
		Link Control 1: CFlE%c CST%c CFE%c <LkFail%c Init%c EOC%c TXO%c <CRCErr=%x
		Link Config 1: MLWI=%1$s DwFcIn%5$c MLWO=%2$s DwFcOut%6$c LWI=%3$s DwFcInEn%7$c LWO=%4$s DwFcOutEn%8$c
		Link Config 1: MLWI=%s MLWO=%s LWI=%s LWO=%s
		Command: WarmRst%c DblEnd%c DevNum=%u ChainSide%c HostHide%c Slave%c <EOCErr%c DUL%c
		Command: WarmRst%c DblEnd%c
		Link Control: CFlE%c CST%c CFE%c <LkFail%c Init%c EOC%c TXO%c <CRCErr=%x IsocEn%c LSEn%c ExtCTL%c 64b%c
		Link Control: CFlE%c CST%c CFE%c <LkFail%c Init%c EOC%c TXO%c <CRCErr=%x
		Link Config: MLWI=%1$s DwFcIn%5$c MLWO=%2$s DwFcOut%6$c LWI=%3$s DwFcInEn%7$c LWO=%4$s DwFcOutEn%8$c
		Link Config: MLWI=%s MLWO=%s LWI=%s LWO=%s
		Flags: PMEClk%c DSI%c D1%c D2%c AuxCurrent=%dmA PME(D0%c,D1%c,D2%c,D3hot%c,D3cold%c)
		Status: D%d NoSoftRst%c PME-Enable%c DSel=%d DScale=%d PME%c
		Status: RQ=%d Iso%c ArqSz=%d Cal=%d SBA%c ITACoh%c GART64%c HTrans%c 64bit%c FW%c AGP3%c Rate=%s
		Command: RQ=%d ArqSz=%d Cal=%d SBA%c AGP%c GART64%c 64bit%c FW%c Rate=%s
Slot ID: %d slots, First%c, chassis %02x
MSI: Enable%c Count=%d/%d Maskable%c 64bit%c
		Masking: %08x  Pending: %08x
		Command: DPERE%c ERO%c RBC=%d OST=%d
		Status: Dev=%02x:%02x.%d 64bit%c 133MHz%c SCD%c USC%c DC=%s DMMRBC=%u DMOST=%u DMCRS=%u RSCEM%c 266MHz%c 533MHz%c
		Secondary Status: 64bit%c 133MHz%c SCD%c USC%c SCO%c SRD%c Freq=%s
		Status: Dev=%02x:%02x.%d 64bit%c 133MHz%c SCD%c USC%c SCO%c SRD%c
		Upstream: Capacity=%u CommitmentLimit=%u
		Downstream: Capacity=%u CommitmentLimit=%u
HyperTransport: Slave or Primary Interface		!!! Possibly incomplete decoding		Link Error 0: <Prot%c <Ovfl%c <EOC%c CTLTm%c
		Link Frequency Capability 0: 200MHz%c 300MHz%c 400MHz%c 500MHz%c 600MHz%c 800MHz%c 1.0GHz%c 1.2GHz%c 1.4GHz%c 1.6GHz%c Vend%c
		Feature Capability: IsocFC%c LDTSTOP%c CRCTM%c ECTLT%c 64bA%c UIDRD%c
		Link Error 1: <Prot%c <Ovfl%c <EOC%c CTLTm%c
		Link Frequency Capability 1: 200MHz%c 300MHz%c 400MHz%c 500MHz%c 600MHz%c 800MHz%c 1.0GHz%c 1.2GHz%c 1.4GHz%c 1.6GHz%c Vend%c
		Error Handling: PFlE%c OFlE%c PFE%c OFE%c EOCFE%c RFE%c CRCFE%c SERRFE%c CF%c RE%c PNFE%c ONFE%c EOCNFE%c RNFE%c CRCNFE%c SERRNFE%c
		Prefetchable memory behind bridge Upper: %02x-%02x
HyperTransport: Host or Secondary Interface		Link Error: <Prot%c <Ovfl%c <EOC%c CTLTm%c
		Link Frequency Capability: 200MHz%c 300MHz%c 400MHz%c 500MHz%c 600MHz%c 800MHz%c 1.0GHz%c 1.2GHz%c 1.4GHz%c 1.6GHz%c Vend%c
		Feature Capability: IsocFC%c LDTSTOP%c CRCTM%c ECTLT%c 64bA%c UIDRD%c ExtRS%c UCnfE%c
HyperTransport: Interrupt Discovery and ConfigurationHyperTransport: Revision ID: %u.%02u
HyperTransport: UnitID ClumpingHyperTransport: Extended Configuration Space AccessHyperTransport: Address MappingHyperTransport: MSI Mapping Enable%c Fixed%c
		Mapping Address Base: %016llx
HyperTransport: X86 (reserved)Vendor Specific Information: Len=%02x <?>
Debug port: BAR=%d offset=%04x
CompactPCI central resource control <?>MSI-X: Enable%c Count=%d Masked%c
		Vector table: BAR=%d offset=%08x
800-1200mV(full-swing)/400-700mV(half-swing)200-400mV(full-swing)/100-200mV(half-swing)O@O@7F@7F@O@ P@@P@0O@O@PO@pO@U@ j@g@g@xg@e@e@c@Y@Y@Y@pY@`Y@X@X@X@X@W@pW@V@7d@w -@2@8@?@F@I@L@O@R@W@]@a@b@g@l@p@t@{@@@@@@@@@@@¶@ƶ@ʶ@ζ@Ӷ@ض@ݶ@@@@@@@	@@@Ӷ@ض@ݶ@@?=
#<o:@@"@)@+@1@:@J@F@@U@X@^@b@p@x@@@@@@@@@@@@@@@@̷@@@ط@@@@@@@@
@@"@'@.@@H@H@H@H@)@)@+@ConfigMemMapped3264	Capabilities: [%03x v%dAdvanced Error ReportingVirtual Channel??%d%c%s%c
		Ctrl:	ArbSelect=%s
		Status:	InProgress%c
		VC%d:	<unreadable>			Arb:			Port Arbitration Table <?>Power Budgeting <?>Root Complex Link		Link%d:				Addr:	%08x%08x
Root Bridge Control Block <?>Vendor Specific Information: ID=%04x Rev=%d Len=%03x <?>
Access Control Services		IOVSta:	Migration%c
		Initial VFs: %d, Total VFs: %d, Number of VFs: %d, 		VF offset: %d, stride: %d, Device ID: %04x
		Supported Page Size: %08x, System Page Size: %08x
		Region %d: Memory at Transaction Processing Hints		Extended requester support		No steering table availableLatency Tolerance Reporting		Max snoop latency: %lldns
		UESta:	DLP%c SDES%c TLP%c FCP%c CmpltTO%c CmpltAbrt%c UnxCmplt%c RxOF%c MalfTLP%c ECRC%c UnsupReq%c ACSViol%c
		UEMsk:	DLP%c SDES%c TLP%c FCP%c CmpltTO%c CmpltAbrt%c UnxCmplt%c RxOF%c MalfTLP%c ECRC%c UnsupReq%c ACSViol%c
		UESvrt:	DLP%c SDES%c TLP%c FCP%c CmpltTO%c CmpltAbrt%c UnxCmplt%c RxOF%c MalfTLP%c ECRC%c UnsupReq%c ACSViol%c
		CESta:	RxErr%c BadTLP%c BadDLLP%c Rollover%c Timeout%c NonFatalErr%c
		CEMsk:	RxErr%c BadTLP%c BadDLLP%c Rollover%c Timeout%c NonFatalErr%c
		AERCap:	First Error Pointer: %02x, GenCap%c CGenEn%c ChkCap%c ChkEn%c
		Caps:	LPEVC=%d RefClk=%s PATEntryBits=%d
		Port Arbitration Table [%x] <?>
Caps:	PATOffset=%02x MaxTimeSlots=%d RejSnoopTrans%c

			Ctrl:	Enable%c ID=%d ArbSelect=%s TC/VC=%02x
			Status:	NegoPending%c InProgress%c
Device Serial Number %02x-%02x-%02x-%02x-%02x-%02x-%02x-%02x
		Desc:	PortNumber=%02x ComponentID=%02x EltType=%s
Desc:	TargetPort=%02x TargetComponent=%02x AssocRCRB%c LinkType=%s LinkValid%c
			Addr:	%02x:%02x.%d  CfgSpace=%08x%08x
Root Complex Internal Link <?>Root Complex Event Collector <?>Multi-Function Virtual Channel <?>		ACSCap:	SrcValid%c TransBlk%c ReqRedir%c CmpltRedir%c UpstreamFwd%c EgressCtrl%c DirectTrans%c
		ACSCtl:	SrcValid%c TransBlk%c ReqRedir%c CmpltRedir%c UpstreamFwd%c EgressCtrl%c DirectTrans%c
Alternative Routing-ID Interpretation (ARI)		ARICap:	MFVC%c ACS%c, Next Function: %d
		ARICtl:	MFVC%c ACS%c, Function Group: %d
Address Translation Service (ATS)		ATSCap:	Invalidate Queue Depth: %02x
		ATSCtl:	Enable%c, Smallest Translation Unit: %02x
Single Root I/O Virtualization (SR-IOV)		IOVCap:	Migration%c, Interrupt Message Number: %03x
		IOVCtl:	Enable%c Migration%c Interrupt%c MSE%c ARIHierarchy%c
Function Dependency Link: %02x
%08x (%s-bit, %sprefetchable)
		VF Migration: offset: %08x, BIR: %x
		Interrupt vector mode supported		Device specific mode supported		Steering table in TPH capability structure		Steering table in MSI-X table		Reserved steering table location		Max no snoop latency: %lldns
x@@@@@ @@@@@؀@@x@@P~@}@{@x@x@x@x@x@x@z@y@100nsFixedWRR32WRR64WRR128??4??5??6??7FixedWRR32WRR64WRR128TWRR128WRR256??6??7ConfigEgressInternaluname() failed: %m%i%i%i%i%i%i<name-too-long>sysfs.path,	Kernel modules:	Kernel driver in use: %s
%s %sDriver:	%s
Module:	%s
Cannot open pcimap file %s: %m/lib/modules/%s/modules.pcimapUnterminated or too long line in %s%s/devices/%04x:%02x:%02x.%d/drivershow_driver: sysfs device name too long, why?+-[%04x:%02x]-\-[%04x:%02x]-%02x.%x-[%02x]--[%02x-%02x]-  %s## %02x.%02x:%d is a bridge from %02x to %02x-%02x
!!! Bridge points to invalid primary bus.!!! Bridge points to invalid bus range.Discovered device %02x:%02x.%d
WARNING: Bus mapping can be reliable only with direct hardware access enabled.
Mapping bus %02x
But it was filtered out.
Summary of buses:
%02x: Entered via %02x:%02x.%d
Primary host busSecondary host bus (?)	%02x.%d Bridge to %02x-%02x <overlap bug> <crossing bug>dump.namehelpKnown PCI access methods:
Known PCI access parameters:
%-20s %s (%s)
Unable to allocate %d bytes of memoryUnknown hardware configuration type %sNo such PCI access method: %s (see `-A help' for a list)Invalid PCI access parameter syntax: %sUnrecognized PCI access parameter: %s (see `-O help' for a list)@@@@@@ @@@@@@@@@`@;/.15 66`707P`8h8 :;<(`<H<p @ BB GHIpp[\8`\h`apPPP @H`x`@ h8	`h	P	0	
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Basic display modes:
-mm		Produce machine-readable output (single -m for an obsolete format)
-t		Show bus tree

Display options:
-v		Be verbose (-vv for very verbose)
-k		Show kernel drivers handling each device
-x		Show hex-dump of the standard part of the config space
-xxx		Show hex-dump of the whole config space (dangerous; root only)
-xxxx		Show hex-dump of the 4096-byte extended config space (root only)
-b		Bus-centric view (addresses and IRQ's as seen by the bus)
-D		Always show domain numbers

Resolving of device ID's to names:
-n		Show numeric ID's
-nn		Show both textual and numeric ID's (names & numbers)
-q		Query the PCI ID database for unknown ID's via DNS
-qq		As above, but re-query locally cached entries
-Q		Query the PCI ID database for all ID's via DNS

Selection of devices:
-s [[[[<domain>]:]<bus>]:][<slot>][.[<func>]]	Show only devices in selected slots
-d [<vendor>]:[<device>]			Show only devices with specified ID's

Other options:
-i <file>	Use specified ID database instead of %s
-p <file>	Look up kernel modules in a given file instead of default modules.pcimap
-M		Enable `bus mapping' mode (dangerous; root only)

PCI access options:
-A <method>	Use the specified PCI access method (see `-A help' for a list)
-O <par>=<val>	Set PCI access parameter (see `-O help' for a list)
-G		Enable PCI access debugging
-H <mode>	Use direct hardware access (<mode> = 1 or 2)
-F <file>	Read PCI configuration dump from a given file
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